Jeff Geerling has been exploring the PCIe bus on the new Raspberry Pi 5 and has documented some interesting things, some rather unexpected like the ability to change the speed of the PCIe bus.
In my recent Adafruit Blog article PCIe Bandwidth, I discuss the generations the specification has gone through and with each one comes an increase in bus speed. Gen 1.0 was the original and defined a 2.5 gigatransfers per second (GT/s) speed. Gen 2.0 defined 5 GT/s and 3.0 8 GT/s on a single lane (which scales up linearly per number of lanes). The bus is backwards compatible, re. a Gen 1.0 device can work in a Gen 2.0 slot. But a Gen 3.0 device may or may not like that it is in a Gen 2.0 slot, depending on it’s function and driver.
There are 5 active PCIe lanes on the Raspberry Pi 5 with four going to the RP1 chip and one is broken out to the new PCIe connector. Jeff states:
By default, all PCIe lanes operate at Gen 2.0 speeds, or about 5 GT/sec per lane. Currently there’s no way to change that default for the RP1 chip’s ‘internal’ lanes, but on the external connector, you can add the following lines inside
/boot/config.txt(and reboot) to upgrade the connection to Gen 3.0 (8 GT/sec, almost double the speed):dtparam=pciex1 dtparam=pciex1_gen=3And yes, you can also downgrade the connection to Gen 1.0 speeds (2.5 GT/sec) if you like.
Why default to PCIe Gen 2.0?
Why is it defaulted to Gen 2.0? Because that’s the speed at which the board could be certified for PCI Express. Even older standards like 2.0 and 3.0 are considered ‘high speed’ interconnects. And with any connection on a board, interference and signal issues can cause problems with higher bandwidth.
Read much more in Jeff’s article here.
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